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gennum corporation p.o. box 489, stn. a, burlington, ontario, canada l7r 3y3 tel. +1 (905) 632-2996 fax. +1 (905) 632-5946 e-mail: info@gennum.com www.gennum.com revision date: november 2000 document no. 522 - 45 - 05 preliminary data sheet gs9023 features ? single chip embedded audio solution operates as an embedded audio multiplexer or demultiplexer full support for 48khz synchronous 20/24 bit audio 4 channels of audio per gs9023 cascadable architecture supports additional audio channels multiplexes and demultiplexes arbitrary anc data packets support for 143, 177, 270, 360 and 540 mb/s video standards full processing of audio parity, channel status and user data multiplexes and demultiplexes audio control packets edh generation and insertion when in multiplex mode 3.3v core with 3.3v or 5v i/o (requires 5v supply) complies with smpte 272m a, b, and c applications sdi embedded audio description the gs9023 is a highly integrated, single chip solution for the multiplexing/demultiplexing of digital audio channels into and out of digital video signals. the gs9023 supports the multiplexing/demultiplexing of 20 or 24 bit synchronous audio data with a 48khz sample rate. audio signals with different sample rates may be sample rate converted to 48khz before and after the gs9023 using audio sample rate converters. each gs9023 supports all the processing required to handle the multiplexing/demultiplexing of four digital audio channels. to simplify system design, the gs9023 seamlessly integrates with common aes/ebu digital audio receivers and transmitters. the cascadable architecture allows for the multiplexing/demultiplexing of additional audio channels with no external glue logic. the gs9023 supports video standards with rates from 143mb/s to 540mb/s. when in multiplex mode, the gs9023 supports the generation and insertion of edh information according to smpte rp165. in combination with gennum?s gs9032, the gs9023 provides a low power, highly integrated two chip solution for sdi transmit applications. in combination with gennum?s gs7005, the gs9023 provides a low power, highly integrated two chip solution for sdi receive applications. the gs9023 requires a 3.3v power supply for internal core logic and a 3.3v or 5v power supply for device i/o. multiplex mode block diagram ordering information part number package temperature GS9023-CFY 100 pin lqfp 0c to 70c convert input data format convert aes/ebu format wcina/b aina/b auxen am[2:0] mpx convert control code add crc safa/b csa/b uda/b vfla/b s/p mpx control registers generate audio packets addr[3:0] cs, we, re data[7:0] audio buffer mpx din[9:0] 10 10 10 10 3 3 8 10 7 8 generate anci area 8 video detection & synchronization vm[2:0] lock arbitrary packet buffer pkt[8:0] mpx 9 b9=b8 9 mpx 10 10 add edh 10 10 dout[9:0] edh_ins mute 3 2 genlinx ? ii gs9023 embedded audio codec
gennum corporation 522 - 45 - 05 2 gs9023 demultiplex mode block diagram convert output data format convert aes/ebu format anci output control code add crc control registers din[9:0] 10 video detection & synchronization 10 dout[9:0] delete anci delete trs 10 trs detect anci 3 lock buferr auxen am[2:0] aouta/b 8 safa/b csa/b uda/b vfla/b p/s audio buffer 10 output arbitrary packet pkt[8:0] 9 10 wcout addr[3:0], cs, we, re 7 8 data[7:0] mute 2 3
gennum corporation 522 - 45 - 05 3 gs9023 pin connections pin descriptions number symbol type description 1, 17, 26, 90 vddint +3.3v power supply pins for core logic. 2-4 vm[2:0] i video standard format. used in conjunction with the trs pin. vm[2] is the msb and vm[0] is the lsb. see table 1 . 5 demux/mux i mode of operation. when set high, the gs9023 operates in demultiplex mode. when set low, the gs9023 operates in multiplex mode. 6-10,12-16 din[9:0] i parallel digital video signal input. din[9] is the msb and din[0] is the lsb. the digital video input should contain trs information. 11, 23, 25, 29, 50, 58, 71, 82, 98, 100 gnd device ground. 18 reset i device reset. active low. 19 wcina i 48khz word clock for channels 1 and 2. used only when operating in multiplex mode and when the audio source is not an aes/ebu data stream. this pin should be grounded when inputting aes/ebu digital audio data or when operating in demultiplex mode. 20 wcinb i 48khz word clock for channels 3 and 4. used only when operating in multiplex mode and when the audio source is not an aes/ebu data stream. this pin should be grounded when inputting aes/ebu digital audio data or when operating in demultiplex mode. pclk din9 din8 din7 din6 din5 din4 din3 din1 d out9 din2 din0 d out0 d out1 d out2 d out3 d out4 d out5 d out6 d out7 d out8 wc ina wc inb vflb vfla a outb a outa a inb a ina wc out auxen safb csa csb uda udb safa mute pkt2 pkt3 pkt8 pkt7 pkt6 pkt5 pkt4 pkt1 pkt0 nc vm2 vm1 vm0 am2 am1 edh_ins trs anci lock nc buferr addr3 addr2 addr1 addr0 data7 data6 data5 data4 data3 data2 data0 data1 19 8 7 6 5 4 3 2 10 27 26 24 25 28 23 22 21 20 19 18 17 16 15 14 13 12 11 37 36 35 34 33 32 31 30 29 50 49 48 47 46 45 44 43 42 41 40 39 38 75 67 68 69 70 71 72 73 74 66 52 51 53 54 55 56 57 58 59 60 61 62 63 64 65 99 100 98 89 90 91 92 93 94 95 96 97 76 77 78 79 80 81 82 83 84 85 86 87 88 gs9023 (top view) gnd aclk gnd vddint gnd v ddio gnd v ddio gnd pkten vddio gnd vddint gnd vddint gnd vddint gnd test test vddio am0 test gnd reset demux/mux re we cs note: the gs9023 dout[9:0] msb to lsb convention is compatible with the gs9022 but reversed with the gs9032 or gs7005. see interconnection with gs9032 or gs7005 section.
gennum corporation 522 - 45 - 05 4 gs9023 21 aina i audio signal input for channels 1 and 2. aes/ebu digital audio data is bi-phase mark encoded. for all non-aes/ebu input modes, bi-phase mark encoding is not required. 22 ainb i audio signal input for channels 3 and 4. aes/ebu digital audio data is bi-phase mark encoded. for all non-aes/ebu input modes, bi-phase mark encoding is not required. 24 pclk i video clock signal input. 27, 28, 75 test - connect to ground. 30 safa i/o start of audio frame indicator for channels 1 and 2. valid only for non-aes/ebu audio formats. this pin should be grounded when inputting aes/ebu audio data. safa is high for audio frame 0 and low for all other audio frames. in multiplex mode, this pin is an input and is supplied by the user. in demultiplex mode, this pin is an output and is generated by the gs9023. 31 safb i/o start of audio frame indicator for channels 3 and 4. valid only for non-aes/ebu audio formats. this pin should be grounded when inputting aes/ebu audio data. safb is set to high for audio frame 0 and low for all other audio frames. in multiplex mode, this pin is an input and is supplied by the user. in demultiplex mode, this pin is an output and is generated by the gs9023. 32 vfla i/o validity flag for channels 1 and 2. valid only for non-aes/ebu audio formats. this pin should be grounded when inputting aes/ebu audio data. vfla is high when audio is invalid and low when audio is valid. in multiplex mode, this pin is an input and is supplied by the user. in demultiplex mode, this pin is an output and is generated by the gs9023. 33 vflb i/o validity flag for channels 3 and 4. valid only for non-aes/ebu audio formats. this pin should be grounded when inputting aes/ebu audio data. vflb is high when audio is invalid and low when audio is valid. in multiplex mode, this pin is an input and is supplied by the user. in demultiplex mode, this pin is an output and is generated by the gs9023. 34 uda i/o user data for channels 1 and 2. valid only for non-aes/ebu audio formats. this pin should be grounded when inputting aes/ebu audio data. in multiplex mode, this pin is an input and is supplied by the user. in demultiplex mode, this pin is an output and is generated by the gs9023. 35 udb i/o user data for channels 3 and 4. valid only for non-aes/ebu audio formats. this pin should be grounded when inputting aes/ebu audio data. in multiplex mode, this pin is an input and is supplied by the user. in demultiplex mode, this pin is an output and is generated by the gs9023. 36 csa i/o channel status for channels 1 and 2. valid only for non-aes/ebu audio formats. this pin should be grounded when inputting aes/ebu audio data. in multiplex mode, this pin is an input and is supplied by the user. in demultiplex mode, this pin is an output and is generated by the gs9023. 37 csb i/o channel status for channels 3 and 4. valid only for non-aes/ebu audio formats. this pin should be grounded when inputting aes/ebu audio data. in multiplex mode, this pin is an input and is supplied by the user. in demultiplex mode, this pin is an output and is generated by the gs9023. 38 auxen i/o extended audio enable. when high, the gs9023 processes 24-bit audio samples. when low, the gs9023 processes 20-bit samples. in multiplex mode, this pin is an input and is supplied by the user. in demultiplex mode, this pin is an output and is generated by the gs9023. 39, 51, 67, 76 vddio +3.3v or +5v power supply pins for device i/os. in order for device i/o to be +5v tolerant vddio must be +5v. device i/o are not +5v tolerant if vddio is +3.3v. pin descriptions (continued) number symbol type description
gennum corporation 522 - 45 - 05 5 gs9023 40-48 pkt[8:0] i/o arbitrary data i/o bus. in multiplex mode, the user must input the arbitrary data packet words starting from the secondary data identification (sdid) to the last user data word (udw) according to smpte 291m. the gs9023 internally converts the data to 10 bits by generating the inversion bit (bit 9). the checksum (cs) word is also generated internally. in demultiplex mode, the gs9023 outputs the arbitrary data packet words starting from the sdid to the last udw. pkt[8] is the msb and pkt[0] is the lsb. see figures 9 and 13 . 49 pkten i/o arbitrary data packet enable. in multiplex mode, pkten must be set high one pclk cycle before arbitrary packet data is input to the device. in demultiplex mode, the output is set high when outputting arbitrary packet data. see figures 9 and 13 . 52, 69 nc n/a no connect. do not connect these pins. 53 wcout o 48khz word clock for channels 1, 2, 3 and 4. valid only when operating in demultiplex mode. 54 aoutb o audio signal output for channels 3 and 4. the aes/ebu digital audio output is bi- phase mark encoded. in all non-aes/ebu modes, the output is not bi-phase mark encoded. 55 aouta o audio signal output for channels 1 and 2. the aes/ebu digital audio output is bi- phase mark encoded. in all non-aes/ebu modes, the output is not bi-phase mark encoded. 56, 57, 59-66 dout[9:0] o parallel digital video signal output. dout[9] is the msb and dout[0] is the lsb. 68 lock o lock indicator. in multiplex mode, when high, the video standard has been identified, the start of a new video frame has been detected and the device is multiplexing audio. note: lock will not be set high unless at least one of the audio channel enable bits is high. see ? chact ? description in table 14. in demultiplex mode, when high, the video standard has been identified, the ? lock ? process selected by ? actsel ? has been validated and the device is demultiplexing audio. see ? actsel ? description in table 15. note: lock remains active regardless of the number of audio samples in the video stream after ? lock ? is achieved. 70 buferr o buffer error. indicates when an internal buffer overflow/underflow error has occurred. valid only when the device is configured to operate in demultiplex mode. note: if an internal buffer overflow/underflow condition occurs, the gs9023 does not mute the audio output. 72-74, 77-81 data[7:0] i/o host interface data bus. data[7] is the msb and data[0] is the lsb. 83 re i read enable for host interface. active low. 84 we i write enable for host interface. active low. 85 cs i chip select for host interface. active low. 86-89 addr[3:0] i host interface address bus. addr[3] is the msb and addr[0] is the lsb. 91 anci i anci selection. valid in demultiplex mode only. when set high, each ancillary data packet with a did corresponding to either the audio packet did, the extended audio packet did or the arbitrary packet did is removed from the video signal. the data contained in the packets are output at the corresponding pins. the various dids are user programmable in the internal registers and are accessible via the host interface. note: when ancillary data packets are deleted, the gs9023 does not recalculate the edh checkwords. when set low, all ancillary data packets remain in the video signal. pin descriptions (continued) number symbol type description
gennum corporation 522 - 45 - 05 6 gs9023 92 trs i trs selection. used in conjunction with the vm[2:0] pins to select video standard format. in multiplex mode, when the trs pin is high, trs is added to a composite video signal. in demultiplex mode, when high, trs is removed from a composite video signal. see table 1. 93 edh_ins i edh insert selection. valid in multiplex mode only. when set high, the gs9023 performs edh functions according to smpte rp165. when set low, edh is not inserted. note: active picture and full field data words are updated from recalculated values but error flag information is replaced with the values programmed in the internal registers via the host interface. 94 mute i audio mute. in multiplex mode, when set high, the embedded audio packets are forced to ? 0 ? . in demultiplex mode, when set high, the output data is forced to ? 0 ? . 95-97 am[2:0] i audio mode format. in multiplex mode, am[2:0] indicates the input audio data format. in demultiplex mode, am[2:0] indicates the output audio data format. am[2] is the msb and am[0] is the lsb. see table 2 . 99 aclk i input audio signal clock (128 fs). synchronous to pclk. note: all unused inputs of the gs9023 should be connected to ground. pin descriptions (continued) number symbol type description
gennum corporation 522 - 45 - 05 7 gs9023 detailed description the gs9023 has two main modes of operation: multiplex mode and demultiplex mode. in multiplex mode, which is selected by setting the demux/mux input pin low, digital audio is embedded into a digital video stream. in demultiplex mode, which is selected by setting the demux/ mux input pin high, digital audio is extracted from a digital video stream. tables 14 and 15 contain host interface register descriptions for the multiplex and demultiplex modes respectively. multiplex mode video clock input a master video clock must be supplied to the pclk pin corresponding to the selected video standard. the supported video input standards and corresponding clock frequencies are listed in table 1. video data input the video data din[9:0] is clocked into the gs9023 on the rising edge of pclk. the video clock frequency must correspond to the video input standard selected. this is done via the ? vsel ? bit of host interface register #0h. when ? vsel ? is low, the video input standard is selected by the vm[2:0] and trs input pins. when ? vsel ? is high, the video input standard is selected by the ? vmod[2:0] ? and ? d2_trs ? bits in host interface register #0h. the supported video input standards are listed in table 1. after the user has specified the video input standard via the vm[2:0] and trs pins or by setting host interface register #0h, the gs9023 performs video standard detection to verify that the input video stream corresponds to the selected standard. when the selected video input standard is verified, the ? vxst ? bit of host interface register #0h is set high. the lock output pin and the ? lock ? bit of host interface register #0h are then set high if at least one of the audio channel enable bits ? chact(4-1) ? of host interface register #1h is high and the start of a video frame is detected. note: the user must ensure that the video input format correctly corresponds to the video format being provided to the gs9023. table 1: video input formats video standard serial digital data rate (mbps) pclk frequency (mhz) vm[2] or ? vmod[2] ? vm[1] or ? vmod[1] ? vm[0] or ? vmod[0] ? trs or ? d2_trs ? 525/d2 (smpte259m) 143 14.3 0000 525/d2 (smpte244m) 143 14.3 0001 525/d1 270 27.0 0010 reserved - - 0011 525/16:9 360 36.0 0100 reserved - - 0101 525/4:4:4:4 (system #1) 540 54.0 0110 reserved - - 0111 625/d2 (with trs) 177 17.7 1000 625/d2 (without trs) 177 17.7 1001 625/d1 270 27.0 1010 reserved - - 1011 625/16:9 360 36.0 1100 reserved - - 1101 625/4:4:4:4 (system #2) 540 54.0 1110 625/4:2:2p (system #4) 540 54.0 1111
gennum corporation 522 - 45 - 05 8 gs9023 video data output the video signal is output at the dout[9:0] pins. the video signal is synchronized to the rising edge of pclk. when the gs9023 is properly configured, audio packets, extended audio packets, audio control packets and arbitrary data packets are multiplexed into the output video signal. when the video signal is a 525 line or 625 line d2 format, trs information is added to the video signal if the trs input pin or the ? d2_trs ? and ? vsel ? bits of host interface register #0h are high. edh packets can also be inserted into the video signal by setting the edh_ins pin high or by setting the ? edhon ? bit high of host interface register #1h. when selected, the gs9023 inserts edh packets according to smpte rp165. note: active picture and full field data words are updated from recalculated values but error flag information is replaced with the values programmed in host interface registers #eh and #fh. note: in the 525/4:4:4:4 video standard, edh packets should not be inserted as this can lead to trs signal corruption. when edh packets are not inserted, the ? edhdel ? bit of host interface register #0h controls the deletion of edh packets. when the ? edhdel ? bit is set low, edh packets are deleted from the incoming video signal. when ? edhdel ? is set high, edh packets pass through the device unchanged. note: ? edhdel ? functionality is valid only when the ? cascade ? bit of host interface register #4h is low. audio clock input a master audio clock (128 fs: 6.144mhz) must be supplied to the aclk pin. this clock must be synchronized with the video signal input to the gs9023. an audio word clock must also be supplied (fs: 48khz) to the wcina/b pins when using non-aes/ebu audio. the two 48khz word clocks must also be synchronized to the video signal. audio data input the serial audio data for channels 1 and 2 are input to the aina pin. the serial audio data for channels 3 and 4 are input to the ainb pin. the gs9023 can multiplex 20 or 24 bit audio data samples. when the auxen pin or bit ? a4on ? of host interface register #1h is high, the device processes 24 bit audio samples. when the auxen pin or ? a4on ? register bit is low, the device processes 20 bit audio samples. on power up, the ? a4on ? bit default is low. the gs9023 offers five predefined audio data input formats, selected via the am[2:0] pins, which are listed in table 2 and illustrated in figure 1. the first four predefined formats relate to non-aes/ebu audio data while the fifth format corresponds to the aes/ebu audio format. the wcina and wcinb pins should be grounded when inputting aes/ebu audio data as they are not used. the gs9023 supports muting of the audio data input. multiplexed audio and extended data packets for all channels are forced to zero when the mute pin or ? mute ? bit of host interface register #4h is set high. control code input when inputting non-aes/ebu audio data, the validity (v), user data (u) and channel status (c) bits of each audio data channel must be input to the corresponding pins (vfla, vflb; uda, udb; csa, csb). the signals must be updated on the rising edge of wcina/b and remain constant for the entire word clock period (64 aclk cycles). when inputting non-aes/ebu audio data, the safa and safb pins must be high for one frame out of 192 frames received to indicate the start of frame condition. when inputting aes/ebu audio data, the control code input pins should be grounded as they are not used. table 2: audio input formats formats wcina/b am[2] am[1] am[0] ain-mode 0 user supplied 000 ain-mode 1 user supplied 001 ain-mode 2 user supplied 010 ain-mode 3 user supplied 011 ain-aes/ebu not used 1 0 0 not used - 1 0 1 not used - 1 1 0 not used - 1 1 1
gennum corporation 522 - 45 - 05 9 gs9023 fig. 1: audio input format timing diagram safa/b aclk (128fs) wcina/b ain-mode0 8 0 lsb left channel 23 lsb 0 7 right channel right channel msb 23 8 ain-mode1 23 23 ain-mode3 6 0 lsb left channel 23 lsb 0 5 right channel right channel msb 23 6 msb msb ain-mode2 lsb left channel 0 23 msb lsb right channel msb 0 lsb 4 msb left channel 0 lsb 4 msb right channel vfla/b uda/b csa/b data ain-aes/ebu 03 lsb 47 8 audio sample word 27 28 29 30 31 msb lsb aes/ebu sub-frame format 03 lsb 4 7 8 audio sample word 27 28 29 30 31 msb lsb synchronization preamble 20bits 24bits validity flag user data channel status parity bit m channel 1 channel 2 channel 1 channel 2 channel 1 channel 2 mwb w w m sub-frame sub-frame frame 0 (start of block) frame 1 frame 2 23 0 23 23
gennum corporation 522 - 45 - 05 10 gs9023 audio data packets the gs9023 can multiplex up to four audio channels. the channels are selectable via the ? chact(4-1) ? bits of host interface register #1h. the audio group (audio packet data id) for each device is configured in ? ad20id[3:0] ? of host interface register #3h. on power up, the four audio channels and audio group 1 are selected by default. note: do not rely on default value. reprogram on power up or reset. the ? cascade ? bit in host interface register #4h controls the manner in which multiplexing is performed. when ? cascade ? is low, the gs9023 deletes all existing ancillary packets. new packets are multiplexed at the first location after the end of active video (eav) in the horizontal ancillary space (hanc). see figure 2 . when ? cascade ? is high, the gs9023 multiplexes packets at the first free location in the horizontal ancillary (hanc) space after the end of active video (eav) if there is sufficient space remaining to insert the packet. the gs9023 does not check if existing audio group samples are present in the video signal. use caution in applications where the video signal contains existing audio packets to avoid adding identical group samples. see figure 3 . the gs9023 assumes that the ancillary space from the first free location is empty to the start of active video (sav). existing ancillary data packets (inserted by previous devices) in the video signal must be contiguous from the beginning of the hanc space or the insertion of a new audio data packet may overwrite existing data. see figure 4 . fig. 2 fig. 3 eav audio group 1 extended audio group 1 sav empty audio group 2 extended audio group 2 video signal before gs9023 eav sav empty audio group 1 (new) video signal after gs9023 insertion of audio group 1 ("cascade" = low) eav audio group 3 extended audio group 3 sav empty audio group 4 extended audio group 4 video signal before gs9023 eav sav empty audio group 3 (new) extended audio group 3 (new) video signal after gs9023 insertion of audio group 3 ("cascade" = high) audio group 3 (old) extended audio group 3 (old) audio group 4 (old) extended audio group 4 (old)
gennum corporation 522 - 45 - 05 11 gs9023 fig. 4 in cases where an audio data packet does not fit inside the remaining hanc space, the audio packet is discarded. in this case, the ? aderr ? bit of host interface register #7h is high indicating an audio packet multiplexing error. the error bit is cleared once accessed by the host interface. by cascading four gs9023 devices, it is possible to multiplex up to 16 audio channels (according to smpte 272) in a component video signal as shown in figure 18. note: in the 525/d1 video format, only 15 channels of 24 bit audio can be multiplexed. cascade operation is not recommended with a composite video signal, as there is insufficient hanc space for more than four channels of audio. audio packet insertion is not guaranteed in this case. the audio data packet structure as described in smpte 272m is shown in figure 5. the audio data packets words are defined as follows: adf: ancillary data flag . the ancillary data flag marks the beginning of an ancillary packet and is automatically generated by the gs9023. did: data id. audio data packets corresponding to an audio group are selected by programming ? a20id[3:0] ? of host interface register #3h for audio groups 1 to 4 as follows: group 1: fh (2ffh) group 2: dh (1fdh) group 3: bh (1fbh) group 4: 9h (2f9h) note: the six most significant bits of the did are internally generated by the gs9023. dbn: data block number. the data block number is used when data blocks within a common data id are to be linked or to distinguish consecutive data blocks within a common data id. the data block number continuously increments from 1 to 255 and is generated automatically by the gs9023. dc: data count. the data count represents the number of user data words to follow (maximum of 255 words). the data count is automatically generated by the gs9023. cs: checksum. the checksum consists of nine bits. the checksum is used to determine the validity of the words data id through user data. it is the sum of the nine least significant bits of the words data id through user data. the checksum is automatically generated by the gs9023. the serial audio data samples, are mapped into three contiguous ancillary data words (x, x+1, x+2) as shown in ta b l e 3 . fig. 5: audio data packet structure with 4 audio channels, 1 audio group eav sav empty extended audio group 2 video signal before gs9023 eav sav empty video signal after gs9023 insertion of audio group 1 ("cascade" = high) audio group 4 (old) audio group 1 (new) extended audio group 2 (old) empty audio group 2 audio group 4 audio group 2 (corrupted) (old) adf* adf* adf* did dbn dc aes 1, ch.1 aes 1, ch.2 aes 1, ch.2 aes 2, ch.1 aes 2, ch.1 aes 2, ch.1 aes 1, ch.2 aes 1, ch.2 aes 1, ch.2 aes 2, ch.1 aes 2, ch.1 aes 2, ch.1 aes 2, ch.2 aes 2, ch.2 aes 2, ch.2 cs * the ancillary data flag, adf, is one word in composite systems (ansi/smpte 259m) and three words in component systems (ansi/smpte 125m). x x+1 x+2 x x+1 x+2 x x+1 x+2 x x+1 x+2 x x+1 x+2 x x+1 x+2 aes 1, ch.1 aes 1, ch.1 aes 1, ch.2
gennum corporation 522 - 45 - 05 12 gs9023 the audio packet data sample bits are defined as follows: z: the z flag is set high at the same sample coincident with the beginning of a new aes channel status block (frame 0) and is otherwise set low. in non-aes/ebu data input formats this bit is set to the value of the safa/b input pins at the rising edge of wcina/b. ch[1:0]: identification of the channels in an audio group as shown in table 4. aud[19:0] : twos complement linearly represented audio data. the audio data is input from the aina and ainb pins. v: aes/ebu sample validity bit. if the audio sample is valid the bit is set low. if the audio sample is invalid, the bit is set high. in non-aes/ebu data input formats, this bit is set to the value of the vfla/b input pins at the rising edge of wcina/b. u: aes/ebu user bit. in non-aes/ebu data input formats, this bit is set to the value of the uda/b input pins at the rising edge of wcina/b. c: aes/ebu audio channel status bit. in non-aes/ebu data input formats this bit is set to the value of the csa/b input pins at the rising edge of wcina/b. p: even parity for the 26 previous bits in the audio data sample (excludes b9 in the first and second words). note: the p bit is not the same as the aes/ebu parity bit. this bit is automatically generated by the gs9023. extended audio data packets the gs9023 can multiplex 20 or 24 bit audio samples. for 24 bit audio samples, the 20 msbs of a 24 bit audio sample are contained in the audio data packets and the 4 lsbs are contained in an extended audio data packet as defined in smpte 272. the extended audio data packet is multiplexed immediately following the corresponding audio data packet. see figure 6 . fig. 6 table 3: audio packet data sample structure bit word x word x+1 word x+2 b9 not b8 not b8 not b8 b8 aud 5 aud 14 p b7 aud 4 aud 13 c b6 aud 3 aud 12 u b5 aud 2 aud 11 v b4 aud 1 aud 10 aud 19 (msb) b3 aud 0 (lsb) aud 9 aud 18 b2 ch 1 (msb) aud 8 aud 17 b1 ch 0 (lsb) aud 7 aud 16 b0 z aud 6 aud 15 table 4: channel identification within the audio groups ch 1 ch 0 group 1 group 2 group 3 group 4 0 0 channel 1 channel 5 channel 9 channel 13 0 1 channel 2 channel 6 channel 10 channel 14 1 0 channel 3 channel 7 channel 11 channel 15 1 1 channel 4 channel 8 channel 12 channel 16 eav sav empty video signal before gs9023 eav empty video signal after gs9023 insertion of audio group 2 & extended audio group 2 ("cascade" = high) audio group 4 (old) audio group 2 (new) extended audio group 2 (new) audio group 4 sav
gennum corporation 522 - 45 - 05 13 gs9023 fig. 7: extended audio data packet structure to select 24 bit audio operation, the user must set the auxen pin or the ? a4on ? bit of host interface register #1h high. when the auxen pin or ? a4on ? bit is high, the gs9023 does not multiplex the audio data packet and the associated extended audio data packet if there is insufficient room for both in the hanc space. in this case, the ? aderr ? bit of host interface register #7h is set high, indicating an audio packet multiplexing error. the error bit is cleared when accessed by the host interface. the audio group (extended packet data id) for each device is configured in ? ad4id[3:0] ? of host interface register #3h. on power up, audio group 1 is selected by default. by cascading four gs9023 devices, it is possible to multiplex up to 16 audio channels (according to smpte 272) in a component video signal as shown in figure 18. note: in the 525/d1 video format, only 15 channels of 24 bit audio can be multiplexed in the cascade configuration. the extended audio data packet structure as described in smpte 272m is shown in figure 7. the extended audio data packets words are defined as follows: adf: ancillary data flag. the ancillary data flag marks the beginning of an ancillary packet and is automatically generated by the gs9023. did: data id. extended audio data packets corresponding to an audio group are selected by programming ? a4id[3:0] ? of host interface register #3h for audio groups 1 to 4 as follows: group 1: eh (1feh) group 2: ch (2fch) group 3: ah (2fah) group 4: 8h (1f8h) note: the six most significant bits of the did are automatically generated by the gs9023. dbn: data block number. the data block number is used when data blocks within a common data id are to be linked or to distinguish consecutive data blocks within a common data id. the data block number continuously increments from 1 to 255 and is generated automatically by the gs9023. dc: data count. the data count represents the number of user data words to follow (maximum of 255 words). the data count is automatically generated by the gs9023. data words: the extended audio data samples are mapped into ancillary data words as shown in table 5. the extended audio packet data sample bits are defined as follows: x[3:0]: auxiliary data from subframe 1. y[3:0]: auxiliary data from subframe 2. a: address pointer. low for channels 1 and 2, and high for channels 3 and 4. this bit is internally generated by the gs9023. cs: checksum. the checksum consists of nine bits. the checksum is used to determine the validity of the words data id through user data. it is the sum of the nine least significant bits of the words data id through user data. the checksum is automatically generated by the gs9023. audio control packets the audio control packet structure is detailed in smpte 272m. the audio group (audio control packet data id) for each device is configured in ? acid[3:0] ? of host interface register #4h. the audio control parameters are configured in host interface registers #ah, #bh, #ch and #dh. the audio control packet multiplexing positions for the various adf* adf* adf* did dbn dc aes 1 ch.1/2 cs * the ancillary data flag, adf, is one word in composite systems (ansi/smpte 259m) and three words in component systems (ansi/smpte 125m). aes 2 ch.3/4 aes 1 ch.1/2 aes 2 ch.3/4 aes 1 ch.1/2 aes 2 ch.3/4 aes 1 ch.1/2 aes 2 ch.3/4 table 5: extended audio packet data sample structure bit anc data word b9 not b8 b8 a b7 y3 (msb) b6 y2 b5 y1 b4 y0 (lsb) b3 x3 (msb) b2 x2 b1 x1 b0 x0 (lsb)
gennum corporation 522 - 45 - 05 14 gs9023 video standards are listed in table 6. in a component video signal, a maximum of 4 audio control packets can be multiplexed in a cascade connection. on power up, audio group 1 is selected by default. the gs9023 determines if multiplexing is possible by searching for the first free location in the hanc space after the signal eav and calculates if there is sufficient remaining space to insert the audio packet. existing ancillary data packets (inserted by previous devices) in the video signal must be contiguous from the beginning of the hanc space or the insertion of a new audio data packet may overwrite existing data. in cases where an audio control data packet does not fit inside the remaining hanc space, the audio control packet is discarded. in this case, the ? acerr ? bit of host interface register #7h is high indicating an audio control packet multiplexing error. the error bit is cleared when accessed by the host interface. the audio control packet structure as described in smpte 272m is shown in figure 8. fig. 8: audio control packet structure the audio control packets words are defined as follows: adf: ancillary data flag. the ancillary data flag marks the beginning of an ancillary packet and is automatically generated by the gs9023. did: data id. audio control packets corresponding to an audio group are selected by programming ? acid[3:0] ? of host interface register #4h for audio groups 1 to 4 as follows: group 1: fh (1efh) group 2: eh (2eeh) group 3: dh (2edh) group 4: ch (1ech) note: the six most significant bits of the did are automatically generated by the gs9023. dbn: data block number. the data block number is used when data blocks within a common data id are to be linked or to distinguish consecutive data blocks within a common data id. the data block number continuously increments from 1 to 255 and is generated automatically by the gs9023. dc: data count. the data count represents the number of data words to follow. the data count has a fixed value of 212h and is automatically generated by the gs9023. af1-2: audio frame number for channels 1 and 2. af3-4: audio frame number for channels 3 and 4. for an audio sampling frequency of 48khz, the audio frame numbers are sequenced from one to five for 525 line video standards and fixed at one for 625 line video standards. the audio frame numbers, af1-2 and af3-4, are automatically generated by the gs9023 and set to the same value. the sequence count is started at one at the first frame after ? lock ? is achieved. rate: sampling frequency. the gs9023 operates at a fixed sampling frequency of 48khz. the audio control packet rate word structure is shown in table 7. table 6: multiplexing positions for audio control packets video standard multiplexing lines horizontal starting position horizontal ending position 525/d2 12/275 795 849 525/d1 12/275 1444 1711 525/16:9 12/275 1924 2283 525/4:4:4:4 12/275 2884 3427 625/d2 8/321 972 1035 625/d1 8/321 1444 1723 625/16:9 8/321 2277 2299 625/4:4:4:4 8/321 2884 3451 625/4:2:2p 15/641 1444 1723 adf* adf* adf* did dbn dc af1-2 af3-4 rate act dela0 dela1 dela2 delb0 delb1 delb2 delc0 delc1 delc2 deld0 deld1 deld2 rsrv rsrv cs * the ancillary data flag, adf, is one word in composite systems (ansi/smpte 259m) and three words in component systems (ansi/smpte 125m). table 7: audio control packet rate word structure bit rate word b9 not b8 b8 not used (fixed to 0) b7 y2 (msb, fixed to 0)
gennum corporation 522 - 45 - 05 15 gs9023 the audio control packet rate word bits are defined as follows: x[2:0], y[2:0]: audio sampling rate for subframe 1 and 2 respectively. fixed at 48khz. async, bsync: set low when each audio channel pair is operating synchronously and set high when operating asynchronously. forced low due to synchronous operation. act: the act word indicates the active group channels. the audio control packet act word structure is shown in ta b l e 8 . the audio control packet act word bits are defined as follows: p: even parity for bits b0 to b7. a(4-1): individual active channel status indicator. the bits correspond directly to the ? chact(4-1) ? bits of host interface register #1h. the bits are set high for each active channel in a given audio group. the correlation of the active channels for the four active audio groups is shown in ta b l e 9 . delx(0-2): indicates the amount of accumulated audio processing delay relative to video, measured in audio sample intervals for each of the channels. positive values indicate that the video leads the audio. the audio control packets delay word structure is shown in table 10. b6 y1 (fixed to 0) b5 y0 (lsb, fixed to 0) b4 bsync b3 x2 (msb, fixed to 0) b2 x1 (fixed to 0) b1 x0 (lsb, fixed to 0) b0 async table 7: audio control packet rate word structure bit rate word table 8: audio control packet act word structure bit act word b9 not b8 b8 p b7 reserved (set to 0) b6 reserved (set to 0) b5 reserved (set to 0) b4 reserved (set to 0) b3 a4 b2 a3 b1 a2 b0 a1 table 9: audio control packet active channel configuration group1 group2 group3 group4 chact 1 channel 1 channel 5 channel 9 channel 13 chact 2 channel 2 channel 6 channel 10 channel 14 chact 3 channel 3 channel 7 channel 11 channel 15 chact 4 channel 4 channel 8 channel 12 channel 16
gennum corporation 522 - 45 - 05 16 gs9023 the audio control packet delay word bits are defined as follows: e: indicates valid audio delay data when set high. corresponds to the ? acdly ? bit of host interface register #dh. dela/b[25:0]: the audio channel pair delay is programmed in bits ? dela/b[25:0] ? of host interface register #ah, #bh, #ch and #dh. dela[25:0] corresponds to the delay for channels 1 and 2. ? delb[25:0] ? corresponds to the delay for channels 3 and 4. rsrv: reserved. the word is fixed at 200h and is automatically generated by the gs9023. cs: checksum. the checksum consists of nine bits. the checksum is used to determine the validity of the words data id through user data. it is the sum of the nine least significant bits of the words data id through user data. the checksum is automatically generated by the gs9023. arbitrary data packets the gs9023 is capable of multiplexing arbitrary data packets according to smpte 291m. typically, this consists of linear time code data (ltc), vertical interval time code data (vitc) or other data which is multiplexed once per field. the user must input the 9 lsbs starting from the secondary data identification (sdid) word to the last user data word (udw) of the ancillary data packet containing arbitrary data. the cs word and bit 10 of all words in the packet are internally generated. the arbitrary data packet data id is configured in ? pktid[7:0] ? of host interface register #5h. to process arbitrary data, the user must set the ? pkon ? bit of host interface register #1h. also, the user must specify the line number in ? pktline[7:0] ? in host interface register #9h. this value corresponds to the line in video field 1 in which the user wants the arbitrary data packet to be multiplexed. the corresponding line in field 2 is automatically selected for arbitrary data packet multiplexing. arbitrary data is typically multiplexed during the active portion of the line in the vertical blanking interval (vbi). care should be taken to avoid selecting a line in the active picture. table 11 lists recommended multiplexing lines according to the video standard. note: in field #1, the line number is offset by one from the value configured in ? pktline[7:0] ? . arbitrary data is input to the gs9023 as shown in figure 9. the data is stored in an internal arbitrary data packet buffer which is cleared at the end of every field. arbitrary data must be written to the buffer before the line number specified in ? pktline[7:0] ? is reached in order for the packet to be multiplexed. data is input to the pkt[8:0] pins and clocked in on the rising edge of pclk. pkten must be set high one pclk cycle before the data at the pkt[8:0] inputs is valid. pkten must go low one pclk cycle before the last user data word (udw) is input to the pkt[8:0] inputs. parity (bit 8) for each udw can be enabled by setting the ? pktprty ? bit of host interface register #8h to high. when ? pktprty ? is high, data input at pkt[8] is overwritten by the parity bit. up to 255 words (253 udws + sdid + dc) can be input and multiplexed once per field. the arbitrary data packet structure as described in smpte 291m is shown in figure 9. table 10: audio control packet delay structure bit delx0 delx1 delx2 b9 not b8 not b8 not b8 b8 dela/b 7 dela/b 16 dela/b 25 (sign) b7 dela/b 6 dela/b 15 dela/b 24 (msb) b6 dela/b 5 dela/b 14 dela/b 23 b5 dela/b 4 dela/b 13 dela/b 22 b4 dela/b 3 dela/b 12 dela/b 21 b3 dela/b 2 dela/b 11 dela/b 20 b2 dela/b 1 dela/b 10 dela/b 19 b1 dela/b 0 (lsb) dela/b 9 dela/b 18 b0 e dela/b 8 dela/b 17
gennum corporation 522 - 45 - 05 17 gs9023 fig. 9: arbitrary data packet input timing diagram the arbitrary data packet words are defined as follows: adf: ancillary data flag. the ancillary data flag marks the beginning of an ancillary packet and is automatically generated by the gs9023. did: data id. configured in ? pktid[7:0] ? of host interface register #5h. the two most significant bits are internally generated by the gs9023. sdid: secondary data id. the secondary data id is handled as user input data. dc: data count. the data count represents the number of user data words to follow, up to a maximum of 255 words. the data count is handled as user input data. for the gs9023 the maximum data count is 253 since the total number of words that can be input is 255 less the sdid and dc words. udw: user data word. cs: checksum. the checksum consists of nine bits. the checksum is used to determine the validity of the words data id through user data. it is the sum of the nine least significant bits of the words data id through user data. the checksum is automatically generated by the gs9023. error detection the gs9023 provides error status information in host interface register #7h as described in table 14. all errors are cleared when host interface register #7h is read. table 11: multiplex position for arbitrary data packet video standard recommended multiplex line horizontal starting position (word #) horizontal ending position (word #) 525/d2 9/272 340 360 525/d1 14/277 0 1439 525/16:9 14/277 0 1919 note: 525/4:4:4:4 and all 625 line video standards are not supported. * horizontal starting position 0 is the first word of the active picture. pclk (i) pkten (i) 1 clk 1 clk valid data pkt[8:0] (i) 1 - the ancillary data flag, adf, is one word in composite systems (ansi/smpte 259m) and three words in component systems (ansi/smpte 125m). 2 - the adf, did and chksum words are automatically generated by the gs9023. adf 1,2 sdid dc did 2 udw udw udw udw udw udw udw cs 2 adf 1,2 adf 1,2 note:
gennum corporation 522 - 45 - 05 18 gs9023 demultiplex mode video clock input a master video clock must be supplied to the pclk pin corresponding to the selected video signal. the supported video input standards and corresponding clock frequencies are listed in table 1. video data input the video data din[9:0] is clocked in to the gs9023 on the rising edge of pclk. the video clock frequency must correspond to the video input standard selected. this can be done with the vm[2:0] and trs input pins or selected via the ? vsel ? bit of host interface register #0h. when ? vsel ? is set high, the video input standard is selected by ? vmod[2:0] ? and ? d2_trs ? in host interface register #0h. the supported video input standards are listed in table 1. after the user has specified the video input standard via the vm[2:0] and trs pins or in host interface register #0h, the gs9023 performs video standard detection to verify that the input video stream corresponds to the selected standard. when the selected video input standard is verified, the ? vxst ? bit of host interface register #0h is set high. the gs9023 then performs a ? lock ? procedure, as selected by the ? actsel ? bit of host interface register #4h, to determine if the audio is synchronous to the video. when ? actsel ? is low, the gs9023 counts the number of audio samples present in a frame or multiple frames, depending on the video standard selected. ? lock ? is achieved if the required number of samples are detected for 48khz synchronous audio. when ? actsel ? is high, the gs9023 ? locks ? by detecting the presence of an audio control packet corresponding to the did configured in ? acid[3:0] ? of host interface register #4h and occurring at the expected line and position as listed in table 6. if the video signal does not contain audio control packets, ? lock ? will not occur. once ? lock ? is achieved the lock output pin and the ? lock ? bit of host interface register #0h are set high and audio demultiplexing begins. the lock output pin and the ? lock ? bit stay active regardless of the number of samples in the video stream after ? lock ? is achieved. the gs9023 drops out of ? lock ? when there are no more packets detected in the video stream. video data output the video signal is output at the dout[9:0] pins. the video signal is synchronized to the rising edge of pclk. the gs9023 is capable of removing audio, extended audio, arbitrary and audio control packets from the video stream. to remove packets, the user must set the anci pin high or set the ? vsel ? and ? adel ? bits of host interface register #0h high. the gs9023 then removes each packet having a did corresponding to either the audio did, the extended audio did or the arbitrary data did stored in the host interface registers from the video stream. see figure 10 . note: the gs9023 passes edh packets through unchanged in the demultiplex mode. if any audio, extended audio, arbitrary or audio control packets are deleted by the gs9023, the edh crc words become invalid. when the anci pin or ? adel ? bit is low, all ancillary data packets remain in the video signal. see figure 11 . trs can also be removed from a 525/625 d2 video signal when the trs pin is set high or the ? vsel ? and ? d2_trs ? bits of host interface register #0h are set high. fig.10 eav sav empty extended audio group 1 video signal before gs9023 sav empty video signal after gs9023 removal of audio group 1 & extended audio group 1 (anci = high or "vsel" and "adel" = high) audio group 1 extended audio group 2 audio group 2 extended audio group 2 (old) empty audio group 2 (old) eav
gennum corporation 522 - 45 - 05 19 gs9023 fig. 11 audio clock input the user must input a master audio clock (128 fs: 6.144mhz) at the aclk clock terminal. this clock must be synchronized with the video signal input to the gs9023. the audio word clock inputs wcina and wcinb must be grounded. audio data output the serial audio data for channels 1 and 2 are output at the aouta pin. the serial audio data for channels 3 and 4 are output at the aoutb pin. both outputs are synchronized to the rising edge of aclk. the gs9023 can demultiplex 20 or 24 bit audio data samples. when 24 bit audio samples are detected, the auxen pin and bit ? a4on ? of host interface register #1h are set high. when 20 bit audio samples are detected the auxen pin and ? a4on ? register bit are set low. when auxen and ? a4on ? are low, bits 4-7 of the aes/ebu output data format are set to ? 0 ? . in the non-aes/ebu formats, bits 0-3 are set to ? 0 ? . see figure 12 . the gs9023 offers five predefined audio data output formats, selected via the am[2:0] pins, which are listed in table 12 and illustrated in figure 12. the first four predefined formats relate to non-aes/ebu audio data while the fifth format corresponds to the aes/ebu audio format. during reset, the audio outputs are forced low. the gs9023 supports muting of the audio data outputs. the output serial audio samples are forced to zero when the mute pin or ? mute ? bit of host interface register #4h are set high. the audio data outputs are also muted when there is no video input signal. eav sav empty video signal before gs9023 sav empty video signal after gs9023 removal of audio group 1 & extended audio group 1 (anci = low or "vsel" = high and "adel" = low) extended audio group 2 audio group 2 extended audio group 2 (old) audio group 2 (old) eav extended audio group 1 audio extended audio group 1 (old) audio group 1 group 1 (old) table 12: audio output formats formats wcout am[2] am[1] am[0] aout-mode 0 active 48khz 000 aout-mode 1 active 48khz 001 aout-mode 2 active 48khz 010 aout-mode 3 active 48khz 011 aout-aes/ebu - 1 0 0 not used - 1 0 1 not used - 1 1 0 not used - 1 1 1
gennum corporation 522 - 45 - 05 20 gs9023 fig. 12: audio data output formats safa/b aclk (128fs) wcout aout-mode0 8 0 lsb left channel 23 lsb 0 7 right channel right channel msb 23 8 aout-mode1 23 23 aout-mode3 6 0 lsb left channel 23 lsb 0 5 right channel right channel msb 23 6 msb msb aout-mode2 lsb left channel 0 23 msb lsb right channel msb 0 lsb 4 msb left channel 0 lsb 4 msb right channel vfla/b uda/b csa/b data aout-aes/ebu 03 lsb 47 8 audio sample word 27 28 29 30 31 msb lsb aes/ebu sub-frame format 03 lsb 4 7 8 audio sample word 27 28 29 30 31 msb lsb synchronization preamble 20bits 24bits validity flag user data channel status parity bit m channel 1 channel 2 channel 1 channel 2 channel 1 channel 2 mwb w w m sub-frame sub-frame frame 0 (start of block) frame 1 frame 2 23 0 23 23
gennum corporation 522 - 45 - 05 21 gs9023 control code output in the non-aes/ebu output formats, the v, u and c bits are output separately from the audio data stream. the bits are output respectively to the vfla/b, uda/b and csa/b pins according to the channel pair to which they belong and change state on the rising edge of wcout. the safa/b output pins are set to high for one audio frame out of 192 frames to mark the start of a block. in the aes/ebu audio output format, the respective pins are not used. detection of audio packets the gs9023 can demultiplex up to four audio channels of an audio group. the audio group (audio packet data id) for each device is configured in ? ad20id[3:0] ? of host interface register #3h. when the corresponding audio packets are found on the active video line, the gs9023 sets the respective ? chact(4-1) ? bits of host interface register #1h. if no corresponding audio packets are found on the active video line, the ? chact(4-1) ? bits are set low. by connecting four gs9023 devices in parallel, it is possible to demultiplex up to 16 audio channels in a component video signal as shown in figure 19. on power up, audio group 1 is selected by default. detection of extended audio packets the gs9023 can demultiplex 20 or 24 bit audio samples. for 24 bit audio samples, the 20 msbs of a 24 bit audio sample are contained in the audio data packets and the 4 lsbs are contained in an extended audio data packet as defined in smpte 272. the audio group (extended packet data id) for each device is configured in ? ad4id[3:0] ? of host interface register #3h. when the corresponding extended audio packets are detected on the active video stream, the gs9023 sets the auxen pin and the ? a4on ? bit of host interface register #1h to high. if no corresponding extended audio packets are found on the active video line, the auxen pin and ? a4on ? bit are set to low. on power up, audio group 1 extended audio packets are selected by default. detection of audio control packets the audio group (audio control packet data id) for each device is configured in ? acid[3:0] ? of host interface register #4h. when the configured id is detected on the designated video lines ( see table 6 ), the ? acon ? bit of host interface register #1h is set. the corresponding audio control parameters are stored in host interface registers #ah, #bh, #ch and #dh. if an audio control packet is not detected or found in non-designated video lines, ? acon ? is set to low. however, the information in the audio control packets found in non-designated lines is considered valid and is stored in host interface registers #ah, #bh, #ch and #dh. on power up, audio group 1 audio control packets are selected by default. detection and output of arbitrary data packets the gs9023 is capable of demultiplexing arbitrary data packets according to smpte 291m. there are no limitations on the number of packets that can be demultiplexed and the packets can be located outside of the vertical blanking interval (vbi). the arbitrary data packet data id is configured in pktid[7:0] of host interface register #5h. when the configured id is detected in the active video or hanc area, data on the pkt[8:0] pins is clocked out on the rising edge of pclk. the gs9023 sets the pkten output pin high, when the data at the pkt[8:0] outputs is valid. pkten is set low when the last user data word (udw) is output from pkt[8:0]. figure 13 shows the output timing. fig. 13: arbitrary data output timing diagram error detection the gs9023 provides error status information in host interface registers #7h, #8h and #9h as described in table 15. register #7 contains error information on audio sampling and crc conditions. register #8 contains error information on audio packet data block number and data count. register #9 contains error information on control packets. errors are cleared when the respective host interface register is read. pclk (i) pkten (o) pkt[8:0] (o) valid data note: 1 - the ancillary data flag, adf, is one word in composite systems (ansi/smpte 259m) and three words in component systems (ansi/smpte 125m). adf 1 sdid dc did x x+1 x+2 x+3 x+n x+(n-1) x+(n-2) chksum adf 1 adf 1 did 1 clk
gennum corporation 522 - 45 - 05 22 gs9023 multiplex and demultiplex modes delay of video and audio the gs9023 can be configured for various audio sample delays with respect to the video signal. the audio sample delay is selected in ? bufsel[1:0] ? of host interface register #6h. table 13 lists the various audio sample delays. host interface the host interface registers allow for device configuration and provide status information. the gs9023 contains sixteen internal registers that are accessible through the host interface. based on the mode of operation the registers have different functionality. in multiplex mode the registers are defined in table 14 and in demultiplex mode the registers are defined in table 15. the asynchronous host interface consists of a 4 bit address bus (addr[3:0]), 8 bit data bus (data[7:0]), read enable (re ), write enable (we ) and chip select (cs ). the host interface access is independent of the pclk or aclk inputs. read and write cycle timing is detailed in figure 16. in a read cycle, cs is driven low t as seconds after a valid address. re is then driven low after t acs seconds for a minimum of t rd seconds. after t gqv seconds, the address register contents are output on the data bus. after a minimum of t rdh seconds, cs is driven high to end the cycle. similarly, in a write cycle, cs is driven low t as seconds after a valid address. we is then driven low after t acs seconds for a minimum of t wd seconds. valid data must be present for a minimum of t ds seconds before we is driven high again. after a minimum of t wdh seconds, cs is driven high to end the cycle. reset reset timing is detailed in figure 17. setting the reset pin to low for a period of t reset seconds forces the audio outputs low and re-initializes the internal control circuitry including returning all host interface register values to their original default values. the reset pin can be used for synchronizing multiple devices. non-standard sample distributions gennum corporation has made every effort to maximize compatibility of the gs9023 with other embedded audio data streams. unfortunately, due to variations in implementations (i.e. non-standard sample distributions) gennum cannot guarantee compatibility with all embedded audio data streams. interconnection with gs9032 or gs7005 the user should pay special attention when laying out the gs9023 to operate with the gs9032 or gs7005. the msb to lsb convention is consistent between the gs9023 and gs9022 but reversed with respect to the gs9032 or gs7005. layout complexity can be minimized by placing the gs9023 and the gs9032 or gs7005 on opposite sides of the printed circuit board (pcb). table 13: audio video delay ? bufsel[1:0] ? mode multiplex (us) demultiplex (us) multiplex/demultiplex connection (us) 0 (70 sample) 875 541 1416 1 (26 sample - default) 250 312 563 2 (20 sample) 187 250 437 note: when the video signal is in d2 format, the delay is fixed at 70 samples (1416 us).
gennum corporation 522 - 45 - 05 23 gs9023 table 14: multiplex mode host interface registers address bit name function r/w default 0h 2-0 vmod[2:0] video standard selection. see table 1 . valid when ? vsel ? is high. used in conjunction with ? d2_trs ? . ? vmod[2] ? is the msb and ? vmod[0] ? is the lsb. r/w 0 3 lock lock indicator. same functionality as the lock pin. when set high, the video standard has been identified, the start of a new video frame has been detected and the device is ready to multiplex audio. note: lock will not be set high unless at least one of the ? chact(4-1) ? bits (address #1h) is high. r0 4 edhdel edh data delete. when set low, existing edh packets are removed from the video stream. when set high, existing edh packets are passed through unless overwritten via the edh_ins pin or the ? edhon ? bit. valid only when ? cascade ? (address #4h bit 7) is low. r/w 0 5 vxst video signal detection flag. set high when the video signal corresponds to standard selected on the vm[2:0] and trs pins or with the ? vmod[2:0] ? and ? d2_trs ? bits. r0 6 d2_trs trs select. same functionality as the trs pin. used to select video standard format.when set high, trs is added to a composite video signal. valid only when ? vsel ? is high. used in conjunction with ? vmod[2:0] ? . r/w 0 7 vsel video input format (external pin/internal register) configuration select. when set low, the video input format is configured via the vm[2:0] and trs pins. when set high, the video input format is configured via the ? vmod[2:0] ? and ? d2_trs ? bits. r/w 0 1h 3-0 chact(4-1) audio channel enable. when set high, the corresponding audio channel is multiplexed into the video signal. ? chact(4) ? is the msb and ? chact(1) ? is the lsb. note: do not rely on default value. reprogram on power up or reset. r/w fh 4 acon audio control packet enable. when high, the audio control packet is multiplexed in the video signal. r/w 0 5 edhon edh packet enable. same functionality as the edh_ins pin. when set high, the gs9023 performs edh functions according to smpte rp165. note: active picture and full field data words are updated from recalculated values but error flag information is replaced with the values programmed in host interface registers #eh and #fh. r/w 0 6 a4on extended audio packet enable. same functionality as the auxen pin. when set high, the extended audio packet is multiplexed in the video signal (24 bit audio). r/w 0 7 pkon arbitrary data packet enable. when set high, an arbitrary data packet is multiplexed in the video signal. r/w 0 2h 7-0 rsv not used. - 3h 3-0 ad20id[3:0] designates the 4 lsbs of the audio data packet did word. the 6 msbs are internally generated. ? ad20id[3] ? is the msb and ? ad20id[0] ? is the lsb. r/w fh 7-4 ad4id[3:0] designates the 4 lsbs of the extended audio data packet did word. the 6 msbs are internally generated. ? ad4id[3] ? is the msb and ? ad4id[0] ? is the lsb. r/w eh
gennum corporation 522 - 45 - 05 24 gs9023 4h 3-0 acid[3:0] designates the 4 lsbs of the audio control packet did word. the 6 msbs are internally generated. ? acid[3] ? is the msb and ? acid[0] ? is the lsb. r/w fh 4 rsv not used. - 5 mute audio mute enable. same functionality as the mute pin. when set high, the multiplexed audio and extended data packets are forced to zero. r/w 0 6 ac34/12 audio control packet channel pair select. when set high, audio control packet delay data for audio channels 3 and 4 is captured in registers ah, bh, ch and dh. when set low, audio control packet delay data for audio channels 1 and 2 is captured in registers #ah, #bh, #ch and #dh. r/w 0 7 cascade cascade select. when set high, the gs9023 device is part of a cascaded architecture. new packets are multiplexed into the video signal starting at the first free location of the hanc space if there is sufficient remaining space to insert the packet. when set low, new packets are multiplexed into the video signal starting after eav. existing ancillary data packets are overwritten and the remaining ancillary space is cleared. r/w 0 5h 7-0 pktid[7:0] designates the 8 lsbs of the arbitrary data packet did word. the 2 msbs are internally generated. ? pktid[7] ? is the msb and ? pktid[0] ? is the lsb. r/w 0 6h 1-0 bufsel[1:0] video/audio delay mode. ? bufsel[1] ? is the msb and ? bufsel[0] ? is the lsb. see table 13 . r/w 0 7-2 rsv not used. - 7h 0 aderr audio data packet multiplexing error. the packet will not be multiplexed because of insufficient room in the hanc space. error is cleared when read. r0 1 acerr audio control packet multiplexing error. the packet will not be multiplexed because of insufficient room in the hanc space. error is cleared when read. r0 7-2 rsv not used. - 8h 0 rsv not used. - 1 pktprty arbitrary data packet parity select. when set high, a parity bit is generated for every user data word (udw) of an arbitrary data packet. this overwrites any data input at the pkt[8] pin. r/w 0 5-2 rsv not used. - 6 axst1/2 audio ch1/2 detection flag. when set high, an audio signal has been detected. r0 7 axst3/4 audio ch3/4 detection flag. when set high, an audio signal has been detected. r0 9h 7-0 pktline[7:0] arbitrary data packet insertion line. designates the horizontal line on which the gs9023 can multiplex arbitrary data packets in the video signal. r/w 0 ah 7-0 dela/b[7:0] audio control packet delay. designates the audio control packet delay data as specified in the smpte 272m standard. ? dela ? corresponds to audio channels 1 and 2, while ? delb ? corresponds to audio channels 3 and 4. ? dela/b[25] ? is the msb and ? dela/b[0] ? is the lsb. r/w 0 bh 7-0 dela/b[15:8] r/w 0 ch 7-0 dela/b[23:16] r/w 0 dh 1-0 dela/b[25:24] r/w 0 2 acsynca/b audio control packet synchronization data. designates the sync mode bits (asx, asy), as defined in smpte 272m (section 14.5), of channels 1/2 or 3/4 of the audio control packet. the bits are selected by ? ac34/12 ? in register #4h. r/w 0 3 acdly audio control packet delay active. designates the ? e ? bit of word ? delx0 ? of an audio control packet as defined in smpte 272 (section 14.7). when set high indicates valid audio delay data. r/w 0 7-4 rsv not used. - table 14: multiplex mode host interface registers (continued) address bit name function r/w default
gennum corporation 522 - 45 - 05 25 gs9023 eh 0 anci_edh edh packet ancillary error flag. error detected here. r/w 0 1 anci_eda edh packet ancillary error flag. error detected already. r/w 0 2 anci_idh edh packet ancillary error flag. internal error detected here. r/w 0 3 anci_ida edh packet ancillary error flag. internal error detected already. r/w 0 4 anci_ues edh packet ancillary error flag. unknown error status. r/w 0 7-5 rsv not used. - fh 0 crcedh_a/b edh packet error flag. ? crcedh_a ? represents full field information. ? crcedh_b ? represents active picture information. see ? ff/ap_a/b ? (bit 7) . r/w 0 1 crceda_a/b edh packet error flag. ? crceda_a ? represents full field information. ? crceda_b ? represents active picture information. see ? ff/ap_a/b ? (bit 7) . r/w 0 2 crcidh_a/b edh packet error flag. ? crcidh_a ? represents full field information. ? crcidh_b ? represents active picture information. see ? ff/ap_a/b ? (bit 7) . r/w 0 3 crcida_a/b edh packet error flag. ? crcida_a ? represents full field information. ? crcida_b ? represents active picture information. see ? ff/ap_a/b ? (bit 7) . r/w 0 4 crcues_a/b edh packet error flag. ? crcues_a ? represents full field information. ? crcues_b ? represents active picture information. see ? ff/ap_a/b ? (bit 7) . r/w 0 5 crcvld_a/b edh packet crc valid flag. ? crcvld_a ? represents full field information. ? crcvld_b ? represents active picture information. see ? ff/ap_a/b ? (bit 7) . r/w 0 6 rsv not used. - 7 ff/ap_a/b full field/active picture select. when set high, the ff (full field) information is displayed in the above mentioned bits. when set low, the ap (active picture) information is displayed. r/w 0 table 14: multiplex mode host interface registers (continued) address bit name function r/w default
gennum corporation 522 - 45 - 05 26 gs9023 table 15: demultiplex mode host interface registers address bit name function r/w default 0h 2-0 vmod[2:0] video standard selection. see table 1 . valid when ? vsel ? is high. used in conjunction with ? d2_trs ? . ? vmod[2] ? is the msb and ? vmod[0] ? is the lsb. r/w 0 3 lock lock indicator. same functionality as the lock pin. when set high, the video standard has been identified, the ? lock ? process selected by ? actsel ? has been validated and the device is ready to demultiplex audio. see ? actsel ? description . r0 4 adel ancillary data delete. same functionality as the anci pin. when set high, each ancillary data packet with a did corresponding to either the audio packet did, the extended audio packet did or the arbitrary packet did is removed from the video signal. when the ? adel ? bit is low, all ancillary data packets remain in the video signal. valid only when ? vsel ? is high. r/w 0 5 vxst video signal detection flag. set high when the video signal corresponds to standard selected on the vm[2:0] and trs pins or with the ? vmod[2:0] ? and ? d2_trs ? bits. r0 6 d2_trs trs select. same functionality as the trs pin. used to select video standard format. when set high, trs is removed from a composite video signal. valid only when ? vsel ? is high. used in conjunction with ? vmod[2:0] ? . r/w 0 7 vsel video input format (external pin/internal register) configuration select. when set low, the video input format is configured via the vm[2:0] and trs pins. when set high, the video input format is configured via the ? vmod[2:0] ? and ? d2_trs ? bits. r/w 0 1h 3-0 chact(4-1) active audio channel flags. when set high, the corresponding audio packets have been detected on the active video line. when set low, no corresponding audio packets have been detected on the active video line. the flags are updated on every video line. r0 4 acon audio control packet flag. when set high, the audio control packet has been detected in the video signal. r0 5 edhon edh flag. when set high, edh data has been detected in the video signal. r0 6 a4on extended audio packet flag. when set high, the extended audio packet has been detected on the active video line (24 bit audio). when set low, no extended audio packet has been detected on the active video line (24 bit audio). r0 7 rsv not used. - 2h 7-0 rsv not used. - 3h 3-0 ad20id[3:0] designates the 4 lsbs of the audio data packet did word. the 6 msbs are internally generated. ? ad20id[3] ? is the msb and ? ad20id[0] ? is the lsb. r/w fh 7-4 ad4id[3:0] designates the 4 lsbs of the extended audio data packet did word. the 6 msbs are internally generated. ? ad4id[3] ? is the msb and ? ad4id[0] ? is the lsb. r/w eh
gennum corporation 522 - 45 - 05 27 gs9023 4h 3-0 acid[3:0] designates the 4 lsbs of the audio control packet did word. the 6 msbs are internally generated. ? acid[3] ? is the msb and ? acid[0] ? is the lsb. r/w fh 4 rsv not used. - 5 mute audio mute enable. same functionality as the mute pin. when set high, the demultiplexed audio and extended packet data are forced to zero. r/w 0 6 actsel audio lock process select. when set high, the gs9023 ? locks ? by detecting the presence of an audio control packet corresponding to the did configured in ? acid[3:0] ? and occurring at the expected line and position as listed in table 6. when set low, the gs9023 ? locks ? by counting the number of audio samples in a frame or multiple frames and validating the number of samples detected based on the video standard. r/w 0 7 rsv not used. - 5h 7-0 pktid[7:0] designates the 8 lsbs of the arbitrary data packet did word. the 2 msbs are internally generated. ? pktid[7] ? is the msb and ? pktid[0] ? is the lsb. r/w 0 6h 1-0 bufsel[1:0] video/audio delay mode. ? bufsel[1] ? is the msb and ? bufsel[0] ? is the lsb. see table 13 . r/w 1h 2 crcadd aes/ebu crc select. when set high, the c bit (channel status information) of each audio sample contains crc information as defined in the aes3-1992 standard. r/w 0 7-3 rsv not used. - 7h 4-0 rsv not used. - 5 samperr sample error. incorrect number of audio samples detected. 8008 audio samples (48khz) in 5 video frames for a 525 line video format. 1920 audio samples (48khz) in 1 video frame for a 625 line video format. r0 6 acrcerr1/2 audio channel 1/2 crc error. r 0 7 acrcerr3/4 audio channel 3/4 crc error. r 0 8h 0 a20dbnerr audio packet dbn error. a dbn discontinuity was detected. r 0 1 a20dcerr audio packet dc error. the number of udw indicated does not match the number of words found in the data packet. r0 2 rsv not used. - 3 a20b9err audio packet inversion bit error. an incorrect bit 9 inversion of bit 8 was detected in the audio packet. r0 7-4 rsv not used. - 9h 0 accdbnerr audio control packet dbn error. a dbn discontinuity was detected. note: when a dbn discontinuity is detected, the vfla/b pins remain valid (low). r0 1 accdcerr audio control packet dc error. the number of udw indicated does not match the number of words found in the audio control packet. r0 3-2 rsv not used. - 4 accb9err audio control packet inversion bit error. an incorrect bit 9 inversion of bit 8 was detected in the audio control packet. r0 6-5 rsv not used. - 7 a4b9err extended audio packet inversion bit error. an incorrect bit 9 inversion of bit 8 was detected in the extended audio packet. r0 table 15: demultiplex mode host interface registers (continued) address bit name function r/w default
gennum corporation 522 - 45 - 05 28 gs9023 ah 7-0 dela/b[7:0] audio control packet delay. designates the audio control packet delay data as specified in the smpte 272m standard. dela corresponds to audio channels 1 and 2, while delb is the corresponds to audio channels 3 and 4. ? dela/b[25] ? is the msb and ? dela/b[0] ? is the lsb. r0 bh 7-0 dela/b[15:8] r0 ch 7-0 dela/b[23:16] r0 dh 1-0 dela/b[25:24] r0 2 acsynca/b audio control packet synchronization data. designates the sync mode bits (asx, asy) as defined in smpte 272m (section 14.5) of channels 1/ 2 or 3/4 of the audio control packet. the bits are selected by ? ac34/ 12 ? . r0 3 acdly audio control packet delay active. designates the ? e ? bit of word ? delx0 ? of an audio control packet as defined in smpte 272 (section 14.7). when high indicates valid audio delay data. r0 4 act1/2 active channel 1/2 flag. r 0 5 act3/4 active channel 3/4 flag. r 0 6 rsv not used. - 7 ac34/12 audio control packet channel pair select. when set high, audio control packet delay data for audio channels 3 and 4 is captured in registers #ah, #bh, #ch and #dh. when set low, audio control packet delay data for audio channels 1 and 2 is captured in registers ah, bh, ch and dh. r/w 0 eh 0 conpro1/2 aes/ebu channel 1/2 consumer/professional status. see aes-3 1992 standard . r0 1 audmod1/2 aes/ebu channel 1/2 normal/non-audio status. see aes-3 1992 standard . r0 4-2 emph1/2[2:0] aes/ebu channel 1/2 emphasis status. ? emph1/2[2] ? is the msb and ? emp1/2[0] ? is the lsb. see aes-3 1992 standard . r0 5 sync1/2 aes/ebu channel 1/2 sync status. see aes-3 1992 standard .r0 7-6 fsel1/2[1:0] aes/ebu channel 1/2 frequency select status. ? fsel1/2[1] ? is the msb and ? fsel1/2[0] ? is the lsb. see aes-3 1992 standard . r0 fh 0 conpro3/4 aes/ebu channel 3/4 consumer/professional status. see aes-3 1992 standard . r0 1 audmod3/4 aes/ebu channel 3/4 normal/non-audio status. see aes-3 1992 standard . r0 4-2 emph3/4[2:0] aes/ebu channel 3/4 emphasis status. ? emph3/4[2] ? is the msb and ? emp3/4[0] ? is the lsb. see aes-3 1992 standard . r0 5 sync3/4 aes/ebu channel 3/4 sync status. see aes-3 1992 standard .r0 7-6 fsel3/4[1:0] aes/ebu channel 3/4 frequency select status. ? fsel3/4[1] ? is the msb and ? fsel3/4[0] ? is the lsb. see aes-3 1992 standard . r0 table 15: demultiplex mode host interface registers (continued) address bit name function r/w default
gennum corporation 522 - 45 - 05 29 gs9023 absolute maximum ratings parameter value i/o supply voltage -0.3 to 7.0v internal supply voltage -0.3 to 4.0v input voltage (any input) -0.3 to v ddio + 0.5v operating temperature 0 c to 70 c storage temperature -65 c to 150 c lead temperature (soldering, 10 sec.) 230 c dc electrical characteristics t a = 0 c to 70 c unless otherwise shown. parameter symbol conditions min typ max units i/o supply voltage v ddio 5v operating range 4.75 5.00 5.25 v i/o supply current i ddio v ddio = 5v; pclk = 54.0 mhz 25 ma i/o supply current i ddio v ddio = 5v; pclk = 27.0 mhz 18 ma i/o supply voltage v ddio 3.3v operating range 3.00 3.30 3.60 v internal supply voltage v ddint 3.00 3.30 3.60 v internal supply current i ddint pclk = 54.0 mhz 67 ma internal supply current i ddint pclk = 27.0 mhz 37 ma input current in -1 - 1 a hi-z output leakage current oz -1 - 1 a output voltage, logic high v oh oh = -3ma v ddio - 0.4 - - v output voltage, logic low v ol ol = 3ma - - 0.4 v input voltage, logic high v ih v ddio = max (5.25v or 3.6v) 2.0 - - v input voltage, logic low v il v ddio = min. (4.75v or 3.0v) --0.8v input capacitance c i ? = 1mhz, v ddio = 0v - - 10 pf output capacitance c o ? = 1mhz, v ddio = 0v - - 10 pf i/o capacitance c io ? = 1mhz, v ddio = 0v - - 10 pf
gennum corporation 522 - 45 - 05 30 gs9023 ac electrical characteristics v ddio = 5v 5%, t a = 0 c to 70 c unless otherwise shown. parameter symbol conditions min typ max units video clock frequency - - 54 mhz video clock pulse width low t pwl 7.4 - - ns video clock pulse width high t pwh 7.4 - - ns video input data setup time t s 3--ns video input data hold time t h 1--ns video output data delay time t od with 10 pf loading - - 13 ns video output data hold time t oh with 10 pf loading 3 - - ns address set up time t as 3--ns chip select set up time t acs 3--ns read data access time t gqv - - 10 ns read data enable time t gqlz 1--ns read data hold time t rdh 1--ns read pulse width t rd 20 - - ns read cycle time t rc 30 - - ns write data set up time t ds 3--ns write data hold time t wdh 1--ns write pulse width t wd 20 - - ns write cycle time t wc 30 - - ns reset pulse width t reset 1--us device latency multiplexer mode demultiplexer mode 13 10 13 10 13 10 pclks
gennum corporation 522 - 45 - 05 31 gs9023 fig. 14: video data input setup & hold times fig. 15: video data output delay & hold times fig. 16: host interface timing diagram fig. 17: reset timing diagram pclk din[9:0] t s t h pclk data valid dout[9:0] t od t oh read cycle write cycle addr[3:0] cs data[7:0] t rc t as we t acs re t gqlz t gqv valid data t rd t rdh t as t acs t wd valid data t wdh t ds t wc vddint vddio t reset reset t reset vddint(min) vddio(min)
gennum corporation 522 - 45 - 05 32 gs9023 fig. 18: multiplex mode cascadable architecture note: in the 525/d1 video format, only 15 channels of 24 bit audio can be multiplexed fig. 19: demultiplex mode parallel architecture note: the group did value set in the gs9023 via the host interface port corresponds to the audio channels to be demultiplexed. p/s s/p pll clk 54mhz 36mhz 27mhz 17.7mhz 14.3mhz audio channels (ch1/2/3/4) audio channels (ch5/6/7/8) audio channels (ch9/10/11/12) audio channels (ch13/14/15/16) din aina ainb pclk wcin aclk dout demux/mux video in video out din aina ainb pclk wcin aclk dout demux/mux din aina ainb pclk wcin aclk dout demux/mux din aina ainb pclk wcin aclk dout demux/mux cpu group did no. s/p pll clk 54mhz 36mhz 27mhz 17.7mhz 14.3mhz cpu video input with 16 ch. audio data din aouta aoutb pclk aclk dout vdd wcout din aouta aoutb pclk aclk dout vdd wcout din aouta aoutb pclk aclk dout vdd wcout din aouta aoutb pclk aclk dout demux/mux vdd wcout 10 10 10 10 10 10 10 10 audio output ch. 1/2 audio output ch. 3/4 audio output ch. 5/6 audio output ch. 7/8 audio output ch. 9/10 audio output ch. 11/12 audio output ch. 13/14 audio output ch. 15/16 128fs(6.144mhz) gs9023 #1 gs9023 #2 gs9023 #3 gs9023 #4 word clock #1 word clock #2 word clock #3 word clock #4 group did no. word clock #1 word clock #2 word clock #3 word clock #4 time demux/mux demux/mux demux/mux
522 - 45 - 05 33 gennum corporation mailing address: p.o. box 489, stn. a, burlington, ontario, canada l7r 3y3 tel. +1 (905) 632-2996 fax. +1 (905) 632-5946 shipping address: 970 fraser drive, burlington, ontario, canada l7l 5p5 gennum japan corporation c-101, miyamae village, 2-10-42 miyamae, suginami-ku tokyo 168-0081, japan tel. +81 (03) 3334-7700 fax. +81 (03) 3247-8839 gennum uk limited 25 long garden walk, farnham, surrey, england gu9 7hx tel. +44 (0)1252 747 000 fax +44 (0)1252 726 523 gennum corporation assumes no responsibility for the use of any circuits described herein and makes no representations that th ey are free from patent infringement. ?copyright july 1999 gennum corporation. all rights reserved. printed in canada. gs9023 packaging information 100 1 16.00 ?.4 16.00 ?.4 14.00 ?.1 14.00 ?.1 1.70 max 1.40 ?.1 0.5 0.18 1.0 ref 0.50 ?.2 12? nom 12? nom 0? min 10? max dimensions in millimetres +0.1 -0.05 0.1 a a view on a-a 0.125 +0.05 -0.025 100 pin lqfp (fy) revision notes: clarified pin descriptions for pins 6-10, 12-16, 19-22, 54, 55, 70, and 91; added a section called non-standard sample distributions? added smpte compliance information to features; added information to the function column of chact(4-1) of table15. for latest product information, visit www.gennum.com document identification preliminary data sheet the product is in a preproduction phase and specifications are subject to change. caution electrostatic sensitive devices do not open packages or handle except at a static-free workstation

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